VLSI and Nanoscale Circuit Design (CAD tools)

A VLSI (Very Large Scale Integration) circuit contains a large number of components that are integrated on a chip to perform specific system functions. The VLSI circuit design process creates a chip layout: the physical arrangement of the components and their interconnections on the chip. This can be a complex process, thus CAD (Computer-Aided Design) tools are used to assist in the design task.

For many years, VLSI circuits have used MOSFET's (Metal-Oxide-Semiconductor Field-Effect Transistors) to implement the various components on a chip. However, as chips continue to shrink in size, the resulting scaling down of component sizes impacts the physical characteristics of MOSFET's. As chips scale from micrometer (10^-6 m) to nanometer (10^-9 m), new devices will need to be constructed to replace MOSFET's. This will also require modification of CAD tool methods to accommodate these new devices.

We have recently started an Institute of Nanotechnology at The University of Tulsa. Please click here for further information on this institute.

Related Courses

EE 4143/6443 - VLSI Design

This is an introductory course on VLSI (Very Large Scale Integration) circuit design and is typically offered every Spring. EE 4143 is the undergraduate version of this course, while EE 6443 is the graduate version of this course. The objective is for each student to be able to design simple digital integrated circuits and to become familiar with computer-aided design tools. Topics to be covered include CMOS devices, VLSI design methodology, and design rules. Students will learn how to use Micromagic, a computer-aided VLSI design tool, and Verilog, a hardware description language. Prerequisites for this course are EE 2163 and 4043: digital systems principles, electronic devices (MOSFETs).

Collaborators

Dr. Dale Teeters
Dr. Mitchell Thornton, Southern Methodist University
Dr. Roger Wainwright

Former Students and Theses

Debarshi Chatterjee, "Overcoming the Thermal Challenge in Deep Submicron Technology through Fast Thermal Floorplanninng and Post Floorplanning Whitespace Reallocation", M.S. Thesis, 2007. Honorable mention award, 10th Annual TU Student Research Colloquium.
Christopher Linnet, "A Comparison of Genetic Algorithm Operator Methods in Binary Decision Diagram Variable Ordering", M.S. Thesis, 2006.
Lun Li, "Channel Height Estimation in VLSI Design Automation", M.S. Thesis, 2002.

Publications

"COOLER- A Fast Multiobjective Fixed-outline Thermal Floorplanner", D. Chatterjee, T.W. Manikas, I. Markov, Proc. 3rd Annual Austin Conf. on Integrated Systems & Circuits (ACISC-08), 2008. (PDF)
"Nanobattery-crossbar system, a promising candidate for future nanoscale data storage", P.C. Utekar, T.W. Manikas, and D. Teeters, Proc 213th ECS (ElectroChemical Society) Meeting, 2008.
"Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells", T.W. Manikas and D. Teeters, Proc. 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL-08), 2008. (PDF)
"Nanoscale Power and Memory Unit Design for Nanoscale Sensor Systems", T.W. Manikas and D. Teeters, Proceedings of the 53rd ISA Int. Instrumentation Symp., 2007. (PDF)
"A Genetic Algorithm for Non-Slicing Floorplan Representation", D. Chatterjee and T.W. Manikas, Proceedings of National Conference on Intelligent Systems (NCIS), 2007. (PDF)
"Power-Density Aware Floorplanning for Reducing Maximum On-Chip Temperature", D. Chatterjee and T.W. Manikas, Proceedings of 18th IASTED International Conference on Modelling and Simulation (ICMS), pp. 319-324, 2007. (PDF)
"A Genetic Algorithm for Binary Decision Diagram Variable Ordering", C.M. Linnet and T.W. Manikas, Proc. 81st AAAS - SWARM Conf., 2006.
"Partitioning Effects on Placement Performance for VLSI Design", T.W. Manikas and G.R. Kane, Proc. 78th Annual AAAS - SWARM Conf., 2003.
"A Genetic Algorithm for Mixed Macro and Standard Cell Placement", T.W. Manikas and M.H. Mickle, Proc. 45th IEEE Int. Midwest Symp. on Circuits and Systems, 2002, p. 115-118. (PDF)
"Channel Height Estimation in VLSI Design", L. Li, T.W. Manikas, and H. Jin, Proc. 45th IEEE Int. Midwest Symp. on Circuits and Systems , 2002, p. 611-614. (PDF)
"Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement", T.W. Manikas and G.R. Kane, Proc. 11th IEEE/ACM Int. Workshop on Logic & Synthesis (IWLS '02), 2002, p. 27-30. (PDF)
"Standard Cell Partition Size Variance and its Effect on Physical Design", T.W. Manikas and G.R. Kane, Proc. 10th IEEE Int. Workshop on Logic & Synthesis (IWLS '01), 2001, p. 265-268. (PDF)
"Genetic Algorithms vs. Simulated Annealing: A Comparison of Approaches for Solving the Circuit Partitioning Problem", T.W. Manikas and J.T. Cain, Tech. Report TR-96-101, University of Pittsburgh, Dept. of Electrical Engineering, May 1996. (PDF)